Senior ASIC Verification Engineer

Gdynia, pomorskie
Stała
Pełny etat

5 dni temu

Welcome!Our Growth is Creating Great Opportunities!Our team is expanding, and we want to hire the most talented people we can. Continued success depends on it! Once you've had a chance to explore our current open positions, apply to the ones you feel suit you best and keep track of both your progress in the selection process, and new postings that might interest you!Thanks for your interest in working on our team!Adtran Sweden is a development organization based on Stockholm that develops integrated circuits (ASIC) for use in Adtran’s networking products. Adtran Sweden also develops SW drivers and software development tools (compiler, debugger and simulator) to support application development for the Adtran ASICs. The organization manages all aspects of ASIC development from product definition, architecture design, functional design, verification, physical implementation and release to manufacturing. In preparation for new projects, Adtran looks to extend the ASIC team. New members will work closely with the team in Stockholm.ResponsibilitiesAn ASIC Verification Engineer implements test environments and test cases to ensure that
the device functionality is according to the specification. This requires close interaction to architects, ASIC designers and SW designers. The verification engineer also writes the Verification Specification where the details of the verification is documented to allow peer review.Verification environments are typically developed in System Verilog or in Python. Use of reference models in C or C++ is common.The work model will be a mixture between remote work from a local Adtran office and regular travels for face to face work with the team in Stockholm.QualificationsDigital Design FundamentalsSolid understanding of digital logic, finite state machines, and synchronous design principles.Familiarity with ASIC design flows.Hardware Description & Verification LanguagesProficiency in SystemVerilog, particularly with UVM (Universal Verification Methodology).Experience with Verilog and optionally VHDL.Verification MethodologiesKnowledge of constrained-random testing, functional coverage, and assertion-based verification.Familiarity with testbench architecture, testplan development, and regression setup.Competence in functional and code coverage collection and analysis.Simulation & Debug ToolsHands-on experience with simulation tools like Synopsys VCS, Cadence Xcelium, or Mentor Questa.Proficient in using waveform viewers and debug tools such as DVE, SimVision, or Verdi.Scripting & AutomationAbility to write automation scripts in Python, Perl, Tcl, or shell to support regression and testbench development.Formal Verification (Optional but Valuable)Experience with formal tools (e.g., JasperGold, VC Formal) and property checking is a plus.Compensation and Benefits (site in Poland)Stable employment conditions based on an employment contract (turnover rate below 4%)1 additional vacation day for all, and 1 extra after 10 years being with usFlexible working hours and hybrid work (presence in the office in Gdynia 3 days a week)English lessons during working hoursInternal training program to support your training needsPaid employee referral programMultisport Card3% employer contribution to PPKPrivate Health Care at Medicover (extended package for employees and possibility to enroll family members)Strong collaborative and friendly work cultureAccess to various sports activities and eventsModern office (well-equipped gym and playroom) close to the SKM/PKM stations

Adtran

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