
Design Verification Engineer - Data Fabric Systems
- Gdańsk, pomorskie
- Stała
- Pełny etat
- Perform pre-Silicon Verification of next generation high performance Microprocessor designs and related IPs Develop, document and execute on verification test plans at unit level of design hierarchy Develop high level language testbench components including stimulus drivers, behavioral models, monitors and checkers in SystemVerilog Develop, simulate and debug directed/random stimulus to ensure design functionality according to specifications
- Minimum of 5 years experience in Digital Design Verification Strong skills with System Verilog and UVM. Good skills with Verilog Exposure to both maintaining an existing Verification Environment as well as creating one from scratch Experience with functional verification tools by VCS, Cadence, Mentor Graphics Experience working in a Unix/Linux environment Good scripting skills (Perl, Shell, Ruby)